The present invention relates to a complementary semiconductor device (hereinafter referred to as "CMOS"), and more particularly to a CMOS, in which an isolation region between two well regions of opposite conductivity types, each including an insulated gate field effect transistor (hereinafter referred to as "MOS transistor"), is made very small in size to make possible a high-speed operation and large scale integration.
A CMOS is low in power dissipation, and can operate at high speed. Accordingly, the CMOS has been widely used in a memory device and a microcomputer, in recent years. An example of the CMOS is described in a Japanese patent application (Post-examination publication No. 62-7,701). The packing density of CMOS is determined by the distance between an N-channel MOS transistor and a P-channel MOS transistor (that is, the sum of d.sub.n and d.sub.p shown in FIG. 1). In order to increase the packing density of CMOS, it is necessary to make the isolation distance at the boundary between two well regions as small as possible.
In a conventional device shown in FIG. 1, in order to prevent the punch through and short channel effect of a parasitic MOS transistor which is formed between a highly-doped N-diffusion layer 7 serving as the source and drain regions of an N-channel MOS transistor and an N-well region 3, it is required to make a distance d.sub.n between the highly-doped N-diffusion layer 7 and one end of a P-well region 2 larger than variations in position of the above end of the P-well region 2 due to the misregistration of mask in a photolithographic process, that is, it is necessary to make the distance d.sub.n larger than several micrometers. Similarly, it is necessary to make large a distance d.sub.p between a highly-doped P-diffusion layer 8 and a P-well region 2. Thus, it is required to make the distance between the N-channel MOS transistor and a P-channel MOS transistor greater than about 5 .mu.m, which makes it difficult to increase the packing density of CMOS. In order to solve this problem, it has been tried to dig a trench at the boundary between the P-well region 2 and the N-well region 3 so that the depth of the trench is greater than the depth of the well regions 2 and 3. However, it is difficult to form a deep trench in a semiconductor body, and moreover crystal defects are generated by the formation of the deep trench. Hence, it has not been put to practical use to dig a deep trench at the boundary between adjacent well regions.